1. Field of the Invention
This invention relates to a composite multi-layer substrate and module using a substrate designed to make high density mounting of electronic components feasible.
2. Description of the Prior Art
Conventionally, package miniaturization has been vigorously carried out as the approach for high density mounting of electronic components. For example, recently the Chip Size Package (CSP) and ultimately bare chip mounting which makes the package itself redundant have been realized. However, each of these is premised on arranging and mounting (flat surface mounting method) a plurality of electronic components in a two-dimensional (surface) array. By simple calculation, the fundamental limitation of not being able to reduce the mounting surface areas to less than the size of the added area of each electronic component is retained.
Therefore, a mounting method using embedded mounting of the electronic components in a substrate (more specifically, not only the substrate face) but also the inner section of the substrate attracts attention.
Hereafter, widely known technologies of embedded mounting and their associated drawbacks will be explained.
As an electronic component embedded structure using an organic system substrate, the electronic components are mounted in the front surface of the organic substrate serving as the core (hereinafter “core substrate”). In the case of multi-layering, a structure which encapsulates electronic components in a dielectric (nonconductive) prepreg resin is known (hereinafter “first prior art example”). Furthermore, a structure in which grooves are formed in an organic system substrate wherein electronic components are embedded is known (hereinafter “second prior art example”).
Furthermore, as for mounting electronic components on the front surface of a core substrate, a structure (hereinafter “third prior art example”) in which holes corresponding to the size of electronic components are drilled in the prepreg and the electronic components are inserted and embedded in the holes of the prepreg when multi-layering or a structure (hereinafter “fourth prior art example”) with embedded sintered components by transfer in organic resin are known.
However, the first prior art example and the fourth prior art example have a drawback of being disadvantageous to thin-sizing the substrate. Also, in the second prior art example and the third prior art example, there is a drawback mentioned which involves the processing cost of the grooves or holes. Moreover, because electronic component heat dissipation countermeasures are not entirely taken into consideration, any of the prior art examples (first through fourth prior art examples) have a drawback causing inconvenience in mounting electronic components especially in regard to heat generation in larger semiconductor chips, etc.
Japanese Laid-Open Patent Application (Kokai) (A) No. S54-008871 (1979) titled “SEMICONDUCTOR DEVICE” discloses that in order to provide a solid electronic clock that is thin-shaped and a small size, while forming a pattern in one side of a printed circuit board, the device is made of a printed circuit board and a semiconductor chip of almost the equivalent thickness by adhering a metal plate to the rear surface, forming a “hole” in one or both directions in the pattern or metal plate and mounting a semiconductor chip in the hole. However, by this prior art example, when performing a resin seal of the semiconductor chip and multi-layering, there is a drawback of having to grind off the excess resin requiring additional work and making manufacturing costs more expensive. Additionally, concerning mounting in a hole and electronic component having multiple electrodes, such as the five-sided electrode, etc., there is a drawback that the type of electronic component which can be mounted has limitations and this constitution was not taken into consideration at all.
Japanese Laid-Open Patent Application (Kokai) (A) No. S61-287194 (1986) titled “CHIP CARRIER FOR USE IN ELECTRONIC DEVICES” discloses elevation of the heat dissipation effect in electronic components. An insulating resin is laminated on a metal core front surface of a printed circuit board with a metal core base. While forming “concave portions” which reach to the metal core of that insulating resin, the device uses the metal core as a heat sink by mounting in the concave portions in order for the rear surface of an electronic component to be in contact to the metal core. This prior art example describes concave portions that are formed so the insulating resin laminated to the metal core rear surface (opposite side of the mounting surface of the electronic components) also reaches the metal core and the heat dissipation effect is elevated.
Japanese Laid-Open Patent Application (Kokai) (A) No. S64-011400 (1989) titled “MULTILAYERED PLATE FOR MOUNTING IC CHIP” discloses a means to dissipate the heat of semiconductor chips from adjacent positions and to provide a multi-layer substrate for mounting semiconductor chips without generating improper bonding with the metal plate for heat dissipation by way of “holes” for semiconductor chip mounting formed in metal foil or a metal sheet. A printed circuit board is used in which the wiring network containing the above-mentioned holes are formed in one side or both sides of a metal base copper clad laminate in which prepreg or copper foil is superimposed. However, in this prior art example, the relationship between the metal foil in the side walls of the holes for mounting semiconductor chips or the height of the metal sheet and the thickness of the semiconductor chips is not defined. In addition, the configuration having taken into consideration heat dissipation of the semiconductor chips is not defined. Further, from the depth relationship of the holes for mounting semiconductor chips and the thickness of the semiconductor chips not being clear, consideration of thin-sizing is regarded to be insufficient. Also, from having to remove the glass cloth (described later) when the holes for mounting semiconductor chips in a printed circuit board are formed, the increased manufacturing cost is readily anticipated.
Japanese Laid-Open Patent Application (Kokai) (A) No. S64-012598(1989) titled “IC CHIP MOUNTING MULTI LAYER BOARD” discloses the use of a metal sheet with a thickness of 0.1-11.0 mm, preferably 0.2-0.5 mm, and with a thermal expansion coefficient of not more than 9×10−6 cm/cm/° C. Although performing surface treatment suitably and improving the adhesive property is mentioned, these can also be considered similar problems (namely, consideration of thin-shaping is insufficient and increased manufacturing cost) relative to the seventh prior art example.
Japanese Laid-Open Patent Application (Kokai) (A) No. H02-122534 (1990) titled “HYBRID INTEGRATED CIRCUIT” discloses a means to provide a hybrid integrated circuit in which high current can flow and miniaturized high density mounting is made possible. The wiring pattern is formed with “openings” for mounting semiconductor chips in a thermoplastic resin plate, and further consists of semiconductor chips and a metal plate of the same thickness arranged on either side of the semiconductor chips. Also, the thermoplastic resin plate in which the wiring layer is formed in a multi-layer is united with another thermoplastic resin plate by means of thermocompression bonding. The lead terminals of the semiconductor chips are inserted in the openings provided between the thermoplastic resin plates formed in the multi-layer wiring layer and electrically connects with the wiring layer. However, in this prior art example, the measures relative to heat dissipation of the semiconductor chips are not clear. Also, the resin seal around the circumference of the semiconductor chips is problematic from thermocompression bonding with the thermoplastic resin plates in which the openings are formed and the thermoplastic resin plates with which the multi-layer wiring layer is formed. When thermocompression bonding is performed in the state of fusing the thermoplastic resin plates, fluctuation of the thickness between layers of the section which forms the multi-layer wiring layer can be anticipated, and electrical specification control can be presumed to be difficult.
Japanese Laid-Open Patent Application (Kokai) (A) No. 2002-111226 titled “COMPOSITE MULTILAYER BOARD AND MODULE FOR USING IT” disclosure is explained below.
FIG. 12A is a cross sectional plan view of the composite multi-layer substrate described in the official gazette. This composite multi-layer substrate 1 has a stacked multi-layer structure of a plurality of layers. The illustrated example has four layers (described later “resin layers”) 2-5 which are composed of resin material. These resin layers 2-5 are common in that all use resin materials, such as epoxy, etc., for the material (so-called glass cloth 7) and only the layer of the resin layer 2 (drawing top layer) is different in the respect that a glass fiber 6 is contained within the braided (knitted) shape of a net as shown in FIG. 12B. The glass cloth 7 is reinforcement for enhancing the physical strength of the composite multi-layer substrate 1. For convenience of explanation hereinafter, while the resin layer 2 which “has” the glass cloth 7 is denoted as “glass cloth layer 2,” the resin layers 3-5 which “do not have” the glass cloth 7 are denoted as “glass clothless layers 3-5.”
Further, this composite multi-layer substrate 1 is bonded to copper foil on the bottommost surface (underside of the glass clothless layer 5) as the mounting side. The conductor pattern of copper foil is created by etching techniques, and the conductor pattern 8 of the required shape is formed. Also, some of the glass cloth layer 2 is eliminated wherein a concavity 9 (It is called a mold cavity whereas an opening is generally closed) is formed and the electronic components 10 (for example, semiconductor chips) are mounted in the concavity 9.
The electronic components 10 “are embedded” by using the inner section of the composite multi-layer substrate 1. Accordingly, other components can be mounted to the composite multi-layer substrate 1 front surface along with components mounted in higher density.
However, since the invention described in the above-mentioned official gazette (tenth prior art example) uses the glass cloth 7 as reinforcement for enhancing the physical strength of the composite multi-layer substrate 1:
There is a problem of ion migration occurring relative to the interface of the glass fiber 6 and the resin (the main material of the glass cloth layer 2), whereby the insulation becomes destroyed depending on the intensity of the electrolysis and resultant deterioration in the electrical properties.
In order to form the concavity 9 for the mold cavity, it is necessary to physically remove some of the resin layer 2. In that case, the glass fiber 6 within the resin layer 2 must be severed. Although such a cutting operation commonly uses precision processing machines, such as laser, etc., truncation errors are undeniable and considerable production time is also required. Moreover, when a plurality of the concavity 9 is required, there is a problem that the production time proportionately increases which incurs higher manufacturing costs.
Therefore, the present invention's purpose is to prevent deterioration of the electrical characteristic accompanying the generation of migration and aiming at reduction of the manufacturing cost by using other reinforcement as a substitute for the glass cloth.